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16k x 16/18 dual-port static ram cy7c026a cy7c036a cypress semiconductor corporation ? 3901 north first street san jose ca 95134 408-943-2600 document #: 38-06046 rev. *a revised december 27, 2002 25/0251 features ? true dual-ported memory cells which allow simulta- neous access of the same memory location 16k x 16 organization (cy7c026a) 16k x 18 organization (cy7c036a) 0.35-micron cmos for optimum speed/power high-speed access: 12 [1] /15/20 ns low operating power ? active: i cc = 180 ma (typical) ? standby: i sb3 = 0.05 ma (typical) fully asynchronous operation automatic power-down expandable data bus to 32/36 bits or more using mas- ter/slave chip select when using more than one device on-chip arbitration logic semaphores included to permit software handshaking between ports int flags for port-to-port communication separate upper-byte and lower-byte control pin select for master or slave commercial and industrial temperature ranges available in 100-pin tqfp pin-compatible and functionally equivalent to idt70261 notes: 1. see page 6 for load conditions. 2. i/o 8 ? i/o 15 for x16 devices; i/o 9 ? i/o 17 for x18 devices. 3. i/o 0 ? i/o 7 for x16 devices; i/o 0 ? i/o 8 for x18 devices. 4. busy is an output in master mode and an input in slave mode. r/w l oe l i/o 8/9l ? i/o 15/17l i/o control address decode a 0l ? a 13l ce l oe l r/w l busy l i/o control ce l interrupt semaphore arbitration sem l int l m/s ub l lb l i/o 0l ? i/o 7/8l r/w r oe r i/o 8/9l ? i/o 15/17r ce r ub r lb r i/o 0l ? i/o 7/8r ub l lb l logic block diagram a 0l ? a 13l true dual-ported ram array a 0r ? a 13r ce r oe r r/w r busy r sem r int r ub r lb r address decode a 0r ? a 13r [2] [2] [3] [3] [4] [4] 14 8/9 8/9 14 8/9 8/9 14 14 for the most recent information, visit the cypress web site at www.cypress.com
cy7c026a cy7c036a document #: 38-06046 rev. *a page 2 of 18 functional description the cy7c026a and cy7c036a are low-power cmos 16k x 16/18 dual-port static rams. various arbitration schemes are included on the devices to handle situations when multiple pro- cessors access the same piece of data. two ports are provid- ed, permitting independent, asynchronous access for reads and writes to any location in memory. the devices can be uti- lized as standalone 16/18-bit dual-port static rams or multiple devices can be combined in order to function as a 32/36-bit or wider master/slave dual-port static ram. an m/s pin is provid- ed for implementing 32/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. application areas include interpro- cessor/multiprocessor designs, communications status buffer- ing, and dual-port video/graphics memory. each port has independent control pins: chip enable (ce ), read or write enable (r/w ), and output enable (oe ). two flags are provided on each port (busy and int ). busy sig- nals that the port is trying to access the same location currently being accessed by the other port. the interrupt flag (int ) per- mits communication between ports or systems by means of a mail box. the semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphore logic is comprised of eight shared latches. only one side can control the latch (semaphore) at any time. control of a semaphore indicates that a shared re- source is in use. an automatic power-down feature is con- trolled independently on each port by the chip enable pin. the cy7c026a and cy7c036a are available in 100-pin thin quad plastic flatpack (tqfp) packages. pin configurations 100-pin tqfp (top view) 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 nc nc nc a 6l a 5l a 4l int l a 2l a 0l gnd m/s a 0r a 1r a 1l a 3l busy r int r a 2r a 3r a 4r a 5r nc nc nc busy l 58 57 56 55 54 53 52 51 cy7c026a (16k x 16) nc nc nc nc i/o 10l i/o 11l i/o 15l i/o 13l i/o 14l gnd i/o 0r vcc i/o 3r gnd i/o 12l i/o 1r i/o 2r i/o 4r i/o 5r i/o 6r nc nc nc nc vcc 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 i/o 9l i/o 8l i/o 7l i/o 6l i/o 5l i/o 4l i/o 0l i/o 2l i/o 1l vcc r/w l ub l lb l gnd i/o 3l sem l ce l a 13l a 12l a 11l a 10l a 9l a 8l a 7l oe l 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 a 6r a 7r a 8r a 9r a 10r a 11r ce r a 13r ub r gnd r/w r gnd i/o 14r lb r a 12r oe r i/o 15r i/o 13r i/o 12r i/o 11r i/o 10r i/o 9r i/o 8r i/o 7r sem r 33 32 31 30 29 28 27 26
cy7c026a cy7c036a document #: 38-06046 rev. *a page 3 of 18 pin configurations (continued) selection guide cy7c026a cy7c036a -12 [1] cy7c026a cy7c036a -15 cy7c026a cy7c036a -20 maximum access time (ns) 12 15 20 typical operating current (ma) 195 190 180 typical standby current for i sb1 (ma) (both ports ttl level) 55 50 45 typical standby current for i sb3 (ma) (both ports cmos level) 0.05 0.05 0.05 top view 100-pin tqfp 100 99 97 98 96 2 3 1 42 41 59 60 61 12 13 15 14 16 4 5 40 39 95 94 17 26 9 10 8 7 6 11 27 28 30 29 31 32 35 34 36 37 38 33 67 66 64 65 63 62 68 69 70 75 73 74 72 71 89 88 86 87 85 93 92 84 nc nc nc a 5l a 4l int l a 2l a 0l busy l gnd int r a 0r a 1l nc nc i/o 11l i/o 12l i/o 16l v cc gnd i/o 1r i/o 2r v cc 90 91 a 3l m/s busy r i/o 15l gnd i/o 13l i/o 14l a 1r a 2r a 3r a 4r nc nc nc i/o 3r i/o 4r i/o 5r i/o 6r nc nc 18 19 20 21 22 23 24 25 83 82 81 80 79 78 77 76 58 57 56 55 54 53 52 51 43 44 45 46 47 48 49 50 i/o 9l i/o 7l i/o 6l i/o 5l i/o 4l i/o 3l i/o 2l i/o 10l gnd i/o 1l i/o 0l oe l sem l v cc ce l ub l lb l a 11l a 10l a 9l a 8l a 7l a 6l i/o 0r i/o 7r i/o 16r i/o 9r i/o 10r i/o 11r i/o 12r i/o 13r i/o 14r gnd i/o 15r oe r r/w r gnd sem r ce r ub r lb r a 11r a 10r a 9r a 8r a 7r a 6r a 5r i/o 8l i/o 17l i/o 8r i/o 17r r/w l cy7c036a (16k x 18) a 13l a 13r a 12l a 12r
cy7c026a cy7c036a document #: 38-06046 rev. *a page 4 of 18 maximum ratings [5] (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.3v to +7.0v dc voltage applied to outputs in high z state ............................................... ? 0.5v to +7.0v dc input voltage [6] ........................................ ? 0.5v to + 7.0v output current into outputs (low)............................. 20 ma static discharge voltage........................................... >2001v latch-up current.................................................... >200 ma note: 5. the voltage on any input or i/o pin cannot exceed the power pin during power-up. 6. pulse width < 20 ns. pin definitions left port right port description ce l ce r chip enable r/w l r/w r read/write enable oe l oe r output enable a 0l ? a 13l a 0r ? a 13r address i/o 0l ? i/o 17l i/o 0r ? i/o 17r data bus input/output sem l sem r semaphore enable ub l ub r upper byte select (i/o 8 ? i/o 15 for x16 devices; i/o 9 ? i/o 17 for x18 devices) lb l lb r lower byte select (i/o 0 ? i/o 7 for x16 devices; i/o 0 ? i/o 8 for x18 devices) int l int r interrupt flag busy l busy r busy flag m/s master or slave select v cc power gnd ground nc no connect operating range range ambient temperature v cc commercial 0 c to +70 c 5v 10% industrial ? 40 c to +85 c 5v 10%
cy7c026a cy7c036a document #: 38-06046 rev. *a page 5 of 18 notes: 7. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . 8. tested initially and after any design or process changes that may affect these parameters. electrical characteristics over the operating range parameter description cy7c026a cy7c036a unit -12 [1] -15 -20 min. typ. max. min. typ. max. min. typ. max. v oh output high voltage (v cc =min., i oh = ? 4.0 ma) 2.4 2.4 2.4 v v ol output low voltage (v cc =min., i oh = +4.0 ma) 0.4 0.4 0.4 v v ih input high voltage 2.2 2.2 2.2 v v il input low voltage 0.8 0.8 0.8 v i oz output leakage current ? 10 10 ? 10 10 ? 10 10 a i cc operating current (v cc = max., i out = 0 ma) outputs disabled com ? l. 195 325 190 285 180 275 ma indust. 215 305 ma i sb1 standby current (both ports ttl level) ce l & ce r v ih , f = f max com ? l. 55 75 50 70 45 65 ma indust. 65 95 ma i sb2 standby current (one port ttl level) ce l | ce r v ih , f = f max com ? l. 125 205 120 180 110 160 ma indust. 135 205 ma i sb3 standby current (both ports cmos level) ce l & ce r v cc ? 0.2v, f = 0 com ? l. 0.05 0.5 0.05 0.5 0.05 0.5 ma indust. 0.05 0.5 ma i sb4 standby current (one port cmos level) ce l | ce r v ih , f = f max [7] com ? l. 115 185 110 160 100 140 ma indust. 125 175 ma capacitance [8] parameter description test conditions max. unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 5.0v 10 pf c out output capacitance 10 pf
cy7c026a cy7c036a document #: 38-06046 rev. *a page 6 of 18 ac test loads (applicable to -12 only) [9] note: 9. test conditions: c = 10 pf. ac test loads and waveforms (a) normal load (load 1) r1 = 893 ? 5v output r2 = 347 ? c= 30 pf v th =1.4v output c= 30 pf (b) th venin equivalent (load 1) (c) three-state delay (load 2) r1 = 893 ? r2 = 347 ? 5v output c= 5pf r th = 250 ? (used for t lz , t hz , t hzwe , & t lzwe including scope and jig) v th =1.4v output c (a) load 1 (-12 only) r = 50 ? z 0 = 50 ? 3.0v gnd 90% 90% 10% 3ns 3 ns 10% all input pulses 0.00 0.1 0 0.20 0.30 0.40 0.50 0.60 0.70 0.80 0.90 1.00 1 0 1 5 20 25 30 35 (b) load derating curve capacitance (pf) ? (ns) for all -12 access times
cy7c026a cy7c036a document #: 38-06046 rev. *a page 7 of 18 switching characteristics over the operating range [10] parameter description cy7c026a cy7c036a unit -12 [1] -15 -20 min. max. min. max. min. max. read cycle t rc read cycle time 12 15 20 ns t aa address to data valid 12 15 20 ns t oha output hold from address change 3 3 3 ns t ace [11] ce low to data valid 12 15 20 ns t doe oe low to data valid 8 10 12 ns t lzoe [12, 13, 14] oe low to low z 3 3 3 ns t hzoe [12, 13, 14] oe high to high z 10 10 12 ns t lzce [12, 13, 14] ce low to low z 3 3 3 ns t hzce [12, 13, 14] ce high to high z 10 10 12 ns t pu [14] ce low to power-up 0 0 0 ns t pd [14] ce high to power-down 12 15 20 ns t abe [11] byte enable access time 12 15 20 ns write cycle t wc write cycle time 12 15 20 ns t sce [11] ce low to write end 10 12 15 ns t aw address valid to write end 10 12 15 ns t ha address hold from write end 0 0 0 ns t sa [11] address set-up to write start 0 0 0 ns t pwe write pulse width 10 12 15 ns t sd data set-up to write end 10 10 15 ns t hd [16] data hold from write end 0 0 0 ns t hzwe [13, 14] r/w low to high z 10 10 12 ns t lzwe [13, 14] r/w high to low z 3 3 3 ns t wdd [15] write pulse to data delay 25 30 45 ns t ddd [15] write data valid to read data valid 20 25 30 ns notes: 10. test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5v, input pulse levels of 0 to 3 .0v, and output loading of the specified i oi /i oh and 30-pf load capacitance. 11. to access ram, ce =l, ub =l, sem =h. to access semaphore, ce =h and sem =l. either condition must be valid for the entire t sce time. 12. at any given temperature and voltage condition for any given device, t hzce is less than t lzce and t hzoe is less than t lzoe . 13. test conditions used are load 3. 14. this parameter is guaranteed but not tested. 15. for information on port-to-port delay through ram cells from writing port to reading port, refer to read timing with busy wa veform. 16. for 15 ns industrial parts t hd min. is 0.5 ns.
cy7c026a cy7c036a document #: 38-06046 rev. *a page 8 of 18 data retention mode the cy7c026a and cy7c036a are designed with battery backup in mind. data retention voltage and supply current are guaranteed over temperature. the following rules ensure data retention: 1. chip enable (ce ) must be held high during data retention, with- in v cc to v cc ? 0.2v. 2. ce must be kept between v cc ? 0.2v and 70% of v cc during the power-up and power-down transitions. 3. the ram can begin operation >t rc after v cc reaches the minimum operating voltage (4.5 volts). notes: 17. test conditions used are load 2. 18. t bdd is a calculated parameter and is the greater of t wdd ? t pwe (actual) or t ddd ? t sd (actual). 19. ce = v cc , v in = gnd to v cc , t a = 25 c. this parameter is guaranteed but not tested. busy timing [17] t bla busy low from address match 12 15 20 ns t bha busy high from address mismatch 12 15 20 ns t blc busy low from ce low 12 15 20 ns t bhc busy high from ce high 12 15 17 ns t ps port set-up for priority 5 5 5 ns t wb r/w high after busy (slave) 0 0 0 ns t wh r/w high after busy high (slave) 11 13 15 ns t bdd [18] busy high to data valid 12 15 20 ns interrupt timing [17] t ins int set time 12 15 20 ns t inr int reset time 12 15 20 ns semaphore timing t sop sem flag update pulse (oe or sem ) 10 10 10 ns t swrd sem flag write to read time 5 5 5 ns t sps sem flag contention window 5 5 5 ns t saa sem address access time 12 15 20 ns switching characteristics over the operating range [10] (continued) parameter description cy7c026a cy7c036a unit -12 [1] -15 -20 min. max. min. max. min. max. timing parameter test conditions [19] max. unit icc dr1 @ vcc dr = 2v 1.5 ma data retention mode 4.5v 4.5v v cc > 2.0v v cc to v cc ? 0.2v v cc ce t rc v ih
cy7c026a cy7c036a document #: 38-06046 rev. *a page 9 of 18 switching waveforms notes: 20. r/w is high for read cycles. 21. device is continuously selected ce = v il and ub or lb = v il . this waveform cannot be used for semaphore reads. 22. oe = v il . 23. address valid prior to or coincident with ce transition low. 24. to access ram, ce = v il , ub or lb = v il , sem = v ih . to access semaphore, ce = v ih , sem = v il . t rc t aa t oha data valid previous data valid data out address t oha read cycle no.1 (either port address access) [20, 21, 22] t ace t lzoe t doe t hzoe t hzce data valid t lzce t pu t pd i sb i cc data out oe ce and lb or ub current read cycle no.2 (either port ce /oe access) [20, 23, 24] ub or lb data out t rc address t aa t oha ce t lzce t abe t hzce t hzce t ace t lzce read cycle no. 3 (either port) [20, 22, 23, 24]
cy7c026a cy7c036a document #: 38-06046 rev. *a page 10 of 18 notes: 25. r/w must be high during all address transitions. 26. a write occurs during the overlap (t sce or t pwe ) of a low ce or sem and a low ub or lb . 27. t ha is measured from the earlier of ce or r/w or (sem or r/w ) going high at the end of write cycle. 28. if oe is low during a r/w controlled write cycle, the write pulse width must be the larger of t pwe or (t hzwe + t sd ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t sd . if oe is high during an r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t pwe . 29. to access ram, ce = v il , sem = v ih . 30. to access upper byte, ce = v il , ub = v il , sem = v ih . to access lower byte, ce = v il , lb = v il , sem = v ih . 31. transition is measured 500 mv from steady state with a 5-pf load (including scope and jig). this parameter is sampled and not 100% tested. 32. during this period, the i/o pins are in the output state, and input signals must not be applied. 33. if the ce or sem low transition occurs simultaneously with or after the r/w low transition, the outputs remain in the high-impedance state. switching waveforms (continued) t aw t wc t pwe t hd t sd t ha ce r/w oe data out data in address t hzoe t sa t hzwe t lzwe write cycle no. 1: r/w controlled timing [25, 26, 27, 28] [31] [31] [28] [29,30] note 32 note 32 t aw t wc t sce t hd t sd t ha ce r/w data in address t sa write cycle no. 2: ce controlled timing [25, 26, 27, 33] [29,30]
cy7c026a cy7c036a document #: 38-06046 rev. *a page 11 of 18 notes: 34. ce = high for the duration of the above timing (both write and read cycle). 35. i/o 0r = i/o 0l = low (request semaphore); ce r = ce l = high. 36. semaphores are reset (available to both ports) at cycle start. 37. if t sps is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpr edictable. switching waveforms (continued) t sop t saa valid adress valid adress t hd data in valid data out valid t oha t aw t ha t ace t sop t sce t sd t sa t pwe t swrd t doe write cycle read cycle oe r/w i/o 0 sem a 0 ? a 2 semaphore read after write timing, either side [34] match t sps a 0l ? a 2l match r/w l sem l a 0r ? a 2r r/w r sem r timing diagram of semaphore contention [35, 36, 37]
cy7c026a cy7c036a document #: 38-06046 rev. *a page 12 of 18 note: 38. ce l = ce r = low. switching waveforms (continued) valid t ddd t wdd match match r/w r data in r data outl t wc address r t pwe valid t sd t hd address l t ps t bla t bha t bdd busy l timing diagram of read with busy (m/s =high) [38] t pwe r/w busy t wb t wh write timing with busy input (m/s =low)
cy7c026a cy7c036a document #: 38-06046 rev. *a page 13 of 18 note: 39. if t ps is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side busy will be asserted. switching waveforms (continued) address match t ps t blc t bhc address match t ps t blc t bhc ce r validfirst: address l,r busy r ce l ce r busy l ce r ce l address l,r busy timing diagram no. 1 (ce arbitration) [39] ce l valid first: address match t ps address l busy r address mismatch t rc or t wc t bla t bha address r address match address mismatch t ps address l busy l t rc or t wc t bla t bha address r right address valid first: busy timing diagram no. 2 (address arbitration) [39] left address valid first:
cy7c026a cy7c036a document #: 38-06046 rev. *a page 14 of 18 notes: 40. t ha depends on which enable pin (ce l or r/w l ) is deasserted first. 41. t ins or t inr depends on which enable pin (ce l or r/w l ) is asserted last. switching waveforms (continued) interrupt timing diagrams write 3fff t wc right side clears int r : t ha read 3fff t rc t inr write 3ffe t wc right side sets int l : left side sets int r : left side clears int l : read 3ffe t inr t rc address r ce l r/w l int l oe l address r r/w r ce r int l address r ce r r/w r int r oe r address l r/w l ce l int r t ins t ha t ins [40] [41] [41] [41] [40] [41]
cy7c026a cy7c036a document #: 38-06046 rev. *a page 15 of 18 architecture the cy7c026a and cy7c036a consist of an array of 16k words of 16 and 18 bits each of dual-port ram cells, i/o and address lines, and control signals (ce , oe , r/w ). these con- trol pins permit independent access for reads or writes to any location in memory. to handle simultaneous writes/reads to the same location, a busy pin is provided on each port. two interrupt (int ) pins can be utilized for port-to-port communica- tion. two semaphore (sem ) control pins are used for allocat- ing shared resources. with the m/s pin, the devices can func- tion as a master (busy pins are outputs) or as a slave (busy pins are inputs). the devices also have an automatic power- down feature controlled by ce . each port is provided with its own output enable control (oe ), which allows data to be read from the device. functional description write operation data must be set up for a duration of t sd before the rising edge of r/w in order to guarantee a valid write. a write operation is controlled by either the r/w pin (see write cycle no. 1 wave- form) or the ce pin (see write cycle no. 2 waveform). re- quired inputs for non-contention operations are summarized in table 1 . if a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; other- wise the data read is not deterministic. data will be valid on the port t ddd after the data is presented on the other port. read operation when reading the device, the user must assert both the oe and ce pins. data will be available t ace after ce or t doe after oe is asserted. if the user wishes to access a semaphore flag, then the sem pin must be asserted instead of the ce pin, and oe must also be asserted. interrupts the upper two memory locations may be used for message passing. the highest memory location (3fff) is the mailbox for the right port and the second-highest memory location (3ffe) is the mailbox for the left port. when one port writes to the other port ? s mailbox, an interrupt is generated to the owner. the interrupt is reset when the owner reads the contents of the mailbox. the message is user defined. each port can read the other port ? s mailbox without resetting the interrupt. the active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. if an application does not require message passing, do not connect the interrupt pin to the processor ? s interrupt request input pin. the operation of the interrupts and their interaction with busy are summarized in table 2. busy the cy7c026a and cy7c036a provide on-chip arbitration to resolve simultaneous memory location access (contention). if both ports ? ce s are asserted and an address match occurs within t ps of each other, the busy logic will determine which port has access. if t ps is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. busy will be asserted t bla after an address match or t blc after ce is taken low. master/slave a m/s pin is provided in order to expand the word width by configuring the device as either a master or a slave. the busy output of the master is connected to the busy input of the slave. this will allow the device to interface to a master device with no external components. writing to slave devices must be delayed until after the busy input has settled (t blc or t bla ), otherwise, the slave chip may begin a write cycle during a contention situation. when tied high, the m/s pin allows the device to be used as a master and, therefore, the busy line is an output. busy can then be used to send the arbitration outcome to a slave. semaphore operation the cy7c026a and cy7c036a provide eight semaphore latches, which are separate from the dual-port memory loca- tions. semaphores are used to reserve resources that are shared between the two ports. the state of the semaphore indicates that a resource is in use. for example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. the left port then verifies its success in setting the latch by reading it. after writing to the semaphore, sem or oe must be deasserted for t sop before attempting to read the semaphore. the semaphore value will be available t swrd + t doe after the rising edge of the sema- phore write. if the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. when the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. if the left side no longer requires the semaphore, a one is written to cancel its request. semaphores are accessed by asserting sem low. the sem pin functions as a chip select for the semaphore latches (ce must remain high during sem low). a 0 ? 2 represents the semaphore address. oe and r/w are used in the same man- ner as a normal memory access. when writing or reading a semaphore, the other address pins have no effect. when writing to the semaphore, only i/o 0 is used. if a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. that semaphore can now only be modified by the side showing zero (the left port in this case). if the left port now relinquishes con- trol by writing a one to the semaphore, the semaphore will be set to one for both sides. however, if the right port had request- ed the semaphore (written a zero) while the left port had con- trol, the right port would immediately own the semaphore as soon as the left port released it. table 3 shows sample sema- phore operations. when reading a semaphore, all sixteen/eighteen data lines output the semaphore value. the read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. if both ports attempt to ac- cess the semaphore within t sps of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore.
cy7c026a cy7c036a document #: 38-06046 rev. *a page 16 of 18 table 1. non-contending read/write inputs outputs ce r/w oe ub lb sem i/o 9 ? i/o 17 i/o 0 ? i/o 8 operation h x x x x h high z high z deselected: power-down x x x h h h high z high z deselected: power-down l l x l h h data in high z write to upper byte only l l x h l h high z data in write to lower byte only l l x l l h data in data in write to both bytes l h l l h h data out high z read upper byte only l h l h l h high z data out read lower byte only l h l l l h data out data out read both bytes x x h x x x high z high z outputs disabled h h l x x l data out data out read data in semaphore flag x h l h h l data out data out read data in semaphore flag h x x x l data in data in write d in0 into semaphore flag x x h h l data in data in write d in0 into semaphore flag l x x l x l not allowed l x x x l l not allowed table 2. interrupt operation example (assumes busy l =busy r =high) left port right port function r/w l ce l oe l a 0 l ? 13 l int l r/w r ce r oe r a 0r ? 13r int r set right int r flag l l x 3fff x x x x x l [43] reset right int r flag x x x x x x l l 3fff h [42] set left int l flag x x x x l [42] l l x 3ffe x reset left int l flag x l l 3ffe h [43] x x x x x table 3. semaphore operation example function i/o 0 ? i/o 17 left i/o 0 ? i/o 17 right status no action 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token right port writes 0 to semaphore 0 1 no change. right side has no write access to semaphore left port writes 1 to semaphore 1 0 right port obtains semaphore token left port writes 0 to semaphore 1 0 no change. left port has no write access to semaphore right port writes 1 to semaphore 0 1 left port obtains semaphore token left port writes 1 to semaphore 1 1 semaphore free right port writes 0 to semaphore 1 0 right port has semaphore token right port writes 1 to semaphore 1 1 semaphore free left port writes 0 to semaphore 0 1 left port has semaphore token left port writes 1 to semaphore 1 1 semaphore free notes: 42. if busy l =l, then no change. 43. if busy r =l, then no change.
cy7c026a cy7c036a document #: 38-06046 rev. *a page 17 of 18 ? cypress semiconductor corporation, 2001. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do i ng so indemnifies cypress semiconductor against all charges. ordering information 16k x16 asynchronous dual-port sram speed (ns) ordering code package name package type operating range 12 [1] cy7c026a-12ac a100 100-pin thin quad flat pack commercial 15 cy7c026a-15ac a100 100-pin thin quad flat pack commercial cy7c026a-15ai a100 100-pin thin quad flat pack industrial 20 CY7C026A-20AC a100 100-pin thin quad flat pack commercial 16k x18 asynchronous dual-port sram speed (ns) ordering code package name package type operating range 12 [1] cy7c036a-12ac a100 100-pin thin quad flat pack commercial 15 cy7c036a-15ac a100 100-pin thin quad flat pack commercial cy7c036a-15ai a100 100-pin thin quad flat pack industrial 20 cy7c036a-20ac a100 100-pin thin quad flat pack commercial package diagram 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-b
cy7c026a cy7c036a document #: 38-06046 rev. *a page 18 of 18 document title: cy7c026a/cy7c036a 16k x 16/18 dual-port static ram document number: 38-06046 rev. ecn no. issue date orig. of change description of change ** 110198 09/29/01 szv change from spec number: 38-00832 to 38-06046 *a 122296 12/27/02 rbi power up requirements added to maximum ratings information

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